Nuclear Science and Techniques

《核技术》(英文版) ISSN 1001-8042 CN 31-1559/TL     2019 Impact factor 1.556
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Nuclear Science and Techniques ›› 2014, Vol. 25 ›› Issue (1): 010405 doi: 10.13538/j.1001-8042/nst.25.010405

• NUCLEAR ELECTRONICS AND INSTRUMENTATION • Previous Articles     Next Articles

Effectiveness and failure modes of error correcting code in industrial 65 nm CMOS SRAMs exposed to heavy ions

TONG Teng , WANG Xiao-Hui , ZHANG Zhan-Gang , DING Peng-Cheng , LIU Jie , LIU Tian-Qi , SU Hong   

  1. 1Institute of Modern Physics, Chinese Academy of Science, Lanzhou, 730000, China
    2University of Chinese Academy of Sciences, Beijing 10049, China
    3Northwest Normal University, Lanzhou, 730000, China
  • Supported by:

    Supported by the National Natural Science Foundation of China (Nos. 11079045 and 11179003) and the Important Direction Project of the CAS Knowledge Innovation Program (No.KJCX2-YW-N27)

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TONG Teng, WANG Xiao-Hui, ZHANG Zhan-Gang, DING Peng-Cheng, LIU Jie, LIU Tian-Qi, SU Hong . Effectiveness and failure modes of error correcting code in industrial 65 nm CMOS SRAMs exposed to heavy ions.Nuclear Science and Techniques, 2014, 25(1): 010405     doi: 10.13538/j.1001-8042/nst.25.010405

Abstract:

Single event upsets (SEUs) induced by heavy ions have been observed in 65 nm SRAMs to quantitatively evaluate the applicability and effectiveness of single-bit error correcting code (ECC) utilizing Hamming Code. The experiment results reveal three interesting phenomena. First, applying ECC does dramatically improve the performance, the SEU cross sections of SRAMs with ECC (at the order of 10??11 cm2/bit) have two orders of magnitude superior than that without ECC (at the order of 10??9 cm2/bit); Second, ineffectiveness of ECC module was detected, which including 1, 2 and 3 bits errors in single word (not Multiple Bit Upsets, MBUs), through deeply analysis, ECC modules in SRAMs are utilizing (12, 8) Hamming code, and it would lose work when 2 bits upset accumulating in one codeword; Third, the probabilities of failure modes which involving 1, 2 and 3 bits errors, are respectively 39.39%, 37.88% and 22.73% in theoretical calculation, and it has a good match with the experimental testing.

Key words: SEU, SRAM, ECC, Hamming code, Effectiveness, Failure modes

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