Nuclear Science and Techniques

《核技术》(英文版) ISSN 1001-8042 CN 31-1559/TL     2019 Impact factor 1.556

Nuclear Science and Techniques ›› 2013, Vol. 24 ›› Issue (4): 040403 doi: 10.13538/j.1001-8042/nst.2013.04.012

• NUCLEAR ELECTRONICS AND INSTRUMENTATION • Previous Articles     Next Articles

A low dead time vernier delay line TDC implemented in an actel flash-based FPGA

QIN Xi1,2  FENG Changqing1,2,*  ZHANG Deliang1,2  ZHAO Lei1,2#br# LIU Shubin1,2  AN Qi1,2   

  1. 1State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China
    2Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China
  • Received:2013-01-20
  • Contact: FENG Changqing E-mail: fengcq@ustc.edu.cn
  • Supported by:

    Supported by State Key Program of National Natural Science of China under Grant No.11079003 and Fundamental Research Funds for the Central Universities (No.WK2030040023, and WK2030040015)

QIN Xi, FENG Changqing, ZHANG Deliang, ZHAO Lei, LIU Shubin, AN Qi. A low dead time vernier delay line TDC implemented in an actel flash-based FPGA.Nuclear Science and Techniques, 2013, 24(4): 040403     doi: 10.13538/j.1001-8042/nst.2013.04.012
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Abstract:

In this paper, a high precision vernier delay line (VDL) TDC (Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented, achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size. The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs. The double delay lines method is employed to cut the dead time in half to improve its performance. As the bin size of the TDC is dependent on temperature, a compensation algorithm is adopted as temperature drift correction, and the TDC shows satisfying performance in a temperature range from –5°C to +55°C.

Key words: Time measurement, Vernier, Time-to-digital convertor, Double delay lines, Compensation