Nuclear Science and Techniques

《核技术》(英文版) ISSN 1001-8042 CN 31-1559/TL     2019 Impact factor 1.556

Nuclear Science and Techniques ›› 2016, Vol. 27 ›› Issue (5): 118 doi: 10.1007/s41365-016-0120-8

• NUCLEAR ELECTRONICS AND INSTRUMENTATION • Previous Articles     Next Articles

ADC evaluation boards design and test framework for LCLS-II precision receiver

Jin Yang 1,2 ,Gang Huang 1 ,Qiang Du 1 , Lawrence Doolittle 1 , John Byrd 1   

  1. 1 Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA
    2 Department of Engineering Physics, Tsinghua University, Beijing 100084, China
  • Contact: Gang Huang E-mail:ghuang@lbl.gov
  • Supported by:

    This work was supported by the US. Department of Energy (DEAC02- 05CH11231) and the China Scholarship Council.

PDF ShareIt Export Citation
Jin Yang, Gang Huang, Qiang Du, Lawrence Doolittle, John Byrd. ADC evaluation boards design and test framework for LCLS-II precision receiver.Nuclear Science and Techniques, 2016, 27(5): 118     doi: 10.1007/s41365-016-0120-8
Citations
Altmetrics

Abstract:

In the low-level RF control field, ADC acquisition accuracy and noise set the boundary of our control ability, making it important to develop low-noise acquisition systems. From the design to test stage, all the noise terms should be understood and characterized. The specific need addressed here is the precision acquisition system for the second Linac Coherent Light Source (LCLS-II), led by SLAC National Accelerator Laboratory. Test circuit boards for the LTC2174 and AD9268 ADCs are designed and fabricated by LBNL. An ADC test framework based on FPGA evaluation board to assess performance has been developed. The ADC test framework includes both DSP (Digital Signal Processing) firmware and processing software. It is useful for low-level RF control and other synchronization projects. Investigating the clock jitter between two channels give us an understanding of that noise source. Working with the test framework, the raw ADC data are transferred to a computer through a Gigabit Ethernet interface. Then short-term error signal can be calculated based on a sine wave fit. By changing low-pass filter bandwidth, relative long-term performance can also be obtained. Amplitude jitter and differential phase jitter are the key issues for ADCs. This paper will report the test results for LTC2174 and AD9268 chips. The integral amplitude jitter is smaller than 0.003 %, and the integral phase noise is smaller than 0:0015 (measured at 47 MHz RF, 100 MHz clock, bandwidth 1 Hz to 100 kHz) for both ADC chips.

Key words: Precision acquisition, LLRF, LTC2174, AD9268, ADC, Framework