Nuclear Techniques ›› 2020, Vol. 43 ›› Issue (8): 80402-080402.doi: 10.11889/j.0253-3219.2020.hjs.43.080402


A random signal emulator for silicon drift detector based FPGA

Nian YU1,2,Yupeng XU1(),Jia HUO1,Yong CHEN1,Weiwei CUI1,Wei LI1,Ziliang ZHANG1,Dawei HAN1,Yusa WANG1,Can CHEN1,2,Yuxuan ZHU1,3,Xiaofan ZHAO1,2   

  1. 1.Key Laboratory of Particle and Astrophysics, Institute of High Energy Physics, Chinese Acɑdemy of Sciences, Beijing 100049, China
    2.School of Physicɑl Sciences, Uniνersity of Chinese Acɑdemy of Sciences, Beijing 100049, China
    3.College of Physics, Jilin University, Changchun 130012, China
  • Received:2020-05-08 Revised:2020-06-22 Online:2020-08-15 Published:2020-08-12
  • Contact: Yupeng XU
  • About author:YU Nian, male, born in 1993, graduated from University of South China in 2016, doctoral student, focusing on nuclear electronics and nuclear detection technology
  • Supported by:
    the Strategic Priority Research Program on Space Science of Chinese Academy of Sciences(XDA15020501)

Abstract: Background

The enhanced X-ray Timing and Polarimetry mission (eXTP) is a space science mission designed to study fundamental physics under extreme conditions of density, gravity and magnetism. The spectroscopic focusing array (SFA) is one of eXTP's four payloads, and its main function is to achieve spectrum and timing measurements with high dynamic range and high signal-to-noise ratio (SNR). The SFA uses multi-pixel silicon drift detector (SDD) as the focal plane detector.


This study aims to design an SDD signal emulator for the performance test of SFA readout electronics.


The field programmable gate array (FPGA) was used as the core device of this emulator, making use of its abundant programmable logic resources to generate multiple groups of oscillatory loops. First of all, the configurable logic blocks inside the FPGA were designed as multiple oscillating rings, and its outputs were XOR-ed as true random numbers generator (TRNG). By Bernoulli trials, the uniform random numbers were converted into exponential pulse sequence. Then, the NIST (National Institute of Standards and Technology) suite was employed to test the quality of the TRNG output. Finally, the time interval distribution and counting rate characteristic of output pulses for the emulator were tested.


The sequence of true random numbers of 1 000 Mbits have passed the NIST randomness test. The time interval of the output pulses for the emulator follows the exponential distribution. The dynamic range of counting rate is 1.6 ks-1 to 813.8 ks-1. The voltage range of the output pulse is 2.5 mV to 50 mV, and the minimum time interval is 9.6 ns. The signal emulator can work steadily for a long time.


The SDD signal emulator proposed in this paper can meet the requirements of performance tests for the SFA readout electronics.

Key words: Silicon drift detector, Signal emulator, True random number generator, Exponential distribution, Field programmable gate array

CLC Number: 

  • TN782