Nuclear Techniques ›› 2017, Vol. 40 ›› Issue (2): 20101-020101.doi: 10.11889/j.0253-3219.2017.hjs.40.020101


Control of field flatness based on FPGA for multi-cell cavity

ZHANG Zhigang1,2, ZHAO Yubin1,2, XU Kai1,2, ZHENG Xiang1,2, LI Zheng1,2, ZHAO Shenjie1,2, CHANG Qiang1,2, HOU Hongtao1,2, LIU Jianfei1,2   

  1. 1. Shanghai Institute of Applied Physics, Chinese Academy of Sciences, Jiading Campus, Shanghai 201800, China;
    2. Shanghai Key Laboratory of Cryogenics & Superconducting RF Technology, Shanghai 201800, China
  • Received:2016-09-05 Revised:2016-11-18 Online:2017-02-10 Published:2017-01-24
  • Supported by:

    Supported by National Natural Science Foundation of China (No.11335014)


Background: The most important processing is division in the algorithm for the field flatness controller on multi-cell cavity. The algorithm in conventional integer division uses multiple subtraction and shift methods to achieve the operation. A lot of clocks are consumed in the subtraction process, and the cycles consuming is not fixed on each cycle of the division. Purpose: This study aims to design a circular unrecoverable divider based on FPGA (Field-Programmable Gate Array). Methods: Improvement is taken for meliorating the program structure and optimizing the time sequences to achieve speedup of the division and same clock cycle for each conventional division. This algorithm is implemented on FPGA chip using QuartusII, simulated and verified by ModelSim toolkits. Results: The stability of field flatness is less than ±1.3% and 35 cycles for each algorithm when it applied in the controller of DLLRF (Digital Low Level Radio Frequency) for the booster of Shanghai Synchrotron Radiation Facility (SSRF). Conclusion: Control of field flatness based on FPGA for multi-cell cavity satisfies all functional requirements, overperforms the design expectations.

Key words: FPGA, Conventional, Divider, Field flatness control, Clock cycle

CLC Number: 

  • TL506