Nuclear Techniques ›› 2015, Vol. 38 ›› Issue (4): 40404-040404.doi: 10.11889/j.0253-3219.2015.hjs.38.040404

• NUCLEAR ELECTRONICS AND INSTRUMENTATION • Previous Articles     Next Articles

Design and implementation of FPGA-based digital and logical signal processing functions of reactor protection system for TMSR

LIU Ye1,2 LIU Zhenbao1,3 HOU Jie1,2   

  1. 1(Shanghai Institute of Applied Physics, Chinese Academy of Sciences, Jiading Campus, Shanghai 201800, China) 2(Key Laboratory of Nuclear Radiation and Nuclear Energy Technology, Chinese Academy of Sciences, Shanghai 201800, China) 3(University of Chinese Academy of Sciences, Beijing 100049, China)
  • Received:2014-08-27 Revised:2014-12-23 Online:2015-04-10 Published:2015-04-09

Abstract: Background: Field Programmable Gate Array (FPGA) can be used to overcome the software common cause failures (CCF), thus is a more and more widely applied to design the Digital Reactor Protection System (DRPS). There are many companies such as State Nuclear Power Automation System Engineering Company (SNPAS, China), RPC Radiy (Ukraine), etc., are doing research on FPGA-based DRPS. Thorium Molten Salt Reactor (TMSR) project plans to do the same work now. Purpose: Digital signal process (analog to digital converter driven, digital filter, and quantitative comparison), logic process (two-out-of-four logic, 2oo4) and data communication are some key components in DRPS design. It is important to test whether FPGA is able to realize these key techniques or not. Methods: First of all, the flash-based FPGA made by Actel Company is selected to design for digital signal process and logic process, and coded by Verilog Hardware Description Language (Verilog HDL, Verilog) under Libero SoC program. Then the Icarus Verilog (iVerilog) program is employed for simulation, and finally the signal waveform is watched by GtkWave program. Hardware test is performed by using FPGA development board together with some necessary chips. Results: Experimental results showed that the digital signal process and logic process were realized in the dedicated FPGA and performed well. Analog to Digital Converter (ADC) driven module was stable and executed as fast as the ADC chip could. Digital filter module made the ADC data much more stable. Quantitative comparison module got expected results accurately. The 2oo4 logic module gave the result immediately when the inputs had 2 or more “1”. It is of most importance that all of these modules worked simultaneously. Conclusion: It is practicable to use flash-based FPGA in DRPS of TMSR project technically due to its non-software common cause failure, fast speed, simplification and parallelism.

Key words: Field Programmable Gate Array (FPGA), Digital Reactor Protection System (DRPS), Logical process, Analog to Digital Converter (ADC)