Nuclear Techniques ›› 2015, Vol. 38 ›› Issue (2): 20404-020404.doi: 10.11889/j.0253-3219.2015.hjs.38.020404

• NUCLEAR ELECTRONICS AND INSTRUMENTATION • Previous Articles     Next Articles

Design and verification of test method for the single event effect in flash-based FPGA

YANG Zhenlei1,2 WANG Xiaohui1,2 SU Hong1 LIU Jie1 YANG Haibo1,2 CHENG Ke1,3 TONG Teng1,2   

  1. 1(Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China) 2(University of Chinese Academy of Sciences, Beijing 100049, China) 3(Northwest Normal University, Lanzhou 730000, China)
  • Received:2014-08-13 Revised:2014-09-08 Online:2015-02-10 Published:2015-02-02

Abstract: Background: With the increased application of Field Programmable Gate Array (FPGA) in the field of spaceflight, Single Event Effect (SEE) of FPGA is attracting more and more attentions recently. Purpose: The aim is to study single event effect in flash-based FPGA manufactured by Microsemi. Methods: VersaTile and RAM Block from the flash-based FPGA are selected as the research object. First of all, the simulation verification of the method was performed by using ModelSim toolkit. Then the experimental tests of FPGA samples were carried out using SEE testbed based on the Heavy Ion Research Facility in Lanzhou (HIRFL). Results and Conclusion: The simulation results verify that the test methods are effective, and the Single Event Upset (SEU) are detected timely and accurately. Experimental results on the SEE test base using 86Kr of HIRFL showed its rationality and validation.

Key words: Field Programmable Gate Array (FPGA), Single Event Effect (SEE), VeasaTile, RAM Block